Hi, I'm Matilda Dingemans

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PennOS

Project Overview

Over the course of the last two months in CIS 5480, Operating Systems Design, I worked with a team of three others to build a full UNIX-like operating system simulator, PennOS, running as a single host process while implementing its own kernel abstractions, scheduler, signals, shell, and file-system interface. The system supports preemptive multitasking using a priority scheduler, process control blocks, job control with signals, zombie reaping through an init process, and a shell capable of spawning, redirecting, and managing concurrent jobs.

Implementation Details

My primary responsibility was the kernel-side process and system-call infrastructure. I designed and implemented large portions of the s_functions and related kernel helpers that expose core OS behavior such as s_spawn, s_waitpid, s_exit, s_sleep, s_nice, and s_kill, allowing user-level programs to safely interact with kernel state without breaking abstraction boundaries. I also co-designed the process control block (PCB) data structure: tracking PIDs, parent/child relationships, open file descriptors, scheduling state, sleep timers, and signal state, and iteratively refined it throughout the project as features such as job control, background execution, and zombie reaping were added.

I implemented PennOS's signal handling layer and terminal control behavior, including correct propagation of Ctrl-C and Ctrl-Z to foreground jobs only, mapping host OS signals to PennOS signals such as P_SIGTERM and P_SIGSTOP, and ensuring stopped processes could later be continued and re-queued. I also wrote the base PennOS shell code, including spawning init and the interactive shell, managing the execution loop, catching and dispatching commands, and coordinating with the scheduler and logger. In addition, I authored the logging system used to validate scheduler correctness at every clock tick.

While I did not implement the FAT filesystem itself, I worked closely with my teammates to integrate the filesystem into the kernel and shell, ensuring that system-call wrappers, file-descriptor inheritance, and redirection semantics worked correctly across process boundaries. This project gave me hands-on experience building a realistic OS kernel abstraction layer, debugging race conditions in multi-threaded schedulers, and designing clean interfaces between kernel, filesystem, and user-level code in a large collaborative codebase.

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Mini Minecraft

Project Overview

This semester-long group project recreated the core mechanics of Minecraft in C++ and OpenGL, enabling players to explore, modify, and extend a procedurally generated voxel world in real time. The engine supports infinite terrain generation, dynamic chunk loading, multithreaded rendering, player physics, block interaction, and extensible features such as custom shaders, biomes, and 3D object voxelization.

My Contributions

Procedural Terrain Generation

I implemented the core terrain height generation system using layered Perlin noise and fractal Brownian motion functions. The system blends multiple noise fields to form grassland and mountain biomes, including ridge functions to create realistic mountain ranges. Each chunk computes block heights independently and fills the correct material layers such as stone, dirt, grass, snow, and water based on biome and elevation.

Multithreaded Chunk Generation and VBO Pipeline

To support real-time exploration of a large world, I designed the engine’s multithreaded terrain pipeline. I added state-tracking enums to each chunk and created a worker system with separate BlockWorker and VBOWorker threads. Chunks are processed through thread-safe work queues with capped thread pools to prevent resource exhaustion. The system ensures that block data is generated in worker threads, while all GPU buffer uploads occur safely on the main thread, enabling stable, high-performance rendering.

OBJ Mesh Voxelization System

For the final milestone, I implemented full support for loading external OBJ meshes and voxelizing them directly into the world. Pressing O opens a file dialog that allows any OBJ file to be imported. I built a new Voxel class that parses and triangulates meshes, normalizes them to a consistent scale, and voxelizes the surface using barycentric sampling. The system spawns objects dynamically relative to the player’s forward direction and reloads affected chunk VBOs so imported objects appear instantly in-world.

System Design Highlights

• Thread-pool-based chunk generation system with bounded work queues and atomic thread counters.
• Procedural terrain using Perlin noise, FBM, biome blending, and ridge functions.
• Custom OBJ voxelization pipeline with surface sampling and chunk-aware VBO reloading.
• Crash-safe GPU upload pipeline that enforces main-thread buffer operations.
• Spiral-based chunk rendering order centered on the player for improved locality.

Technologies

• C++ / OpenGL / GLSL
• Qt Framework
• Multithreading with std::thread and atomic synchronization
• Procedural generation with Perlin noise & FBM
• OBJ parsing, triangulation, and voxel surface sampling

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SRAM Memory Array

Project Overview

This project involved the full custom design and validation of a 16x4 Static Random-Access Memory (SRAM) array in Cadence for ESE 5700: Digital Integrated Circuits and VLSI Fundamentals. The final memory supports random-access read and write operations across 16 addressable locations with a 4-bit data bus. The complete design was implemented at the transistor level, simulated in Cadence Virtuoso, and verified for functionality, timing, power, and area.

System Architecture

The SRAM array consists of 64 six-transistor (6T) bitcells organized into 16 rows and 4 columns, along with supporting peripheral circuitry including a row decoder, precharge logic, clock-synchronized wordline generation, and tristate read/write drivers. Each memory operation is coordinated using a clock signal to ensure that precharge occurs during the first half of the cycle and wordlines are only asserted during the second half, preventing data corruption.

Key Circuit Blocks

SRAM Bitcell

Each memory cell is built from two cross-coupled CMOS inverters forming a bistable latch, with two NMOS access transistors connecting the internal storage nodes to the complementary bitlines. The cell stores data indefinitely while power is applied and supports nondestructive reads and reliable writes through controlled wordline activation.

Row Decoder

A 4-to-16 row decoder selects the active wordline using a predecoded NAND2/NOR2 architecture rather than naive NAND4 gates, reducing redundant logic, transistor count, and power consumption. This optimized structure significantly improves efficiency while maintaining correct decode behavior across all addresses.

Precharge Circuitry

The precharge network ensures that all bitlines are charged to VDD before each read operation. To avoid large fan-in delay, the design replaces a single NOR16 gate with four NOR4 gates feeding a NAND4 stage. Precharge is enabled only when all wordlines are low and write-enable is inactive.

Read / Write Drivers

Tristate buffer and inverter structures control whether data is driven onto the bitlines (write mode) or read from them (read mode). During writes, the data bus actively forces BL/BLB, while during reads, the bitcells condition the bitlines and the output buffer captures the stored value.

Timing and Performance

Worst-case access time occurs during a read-0 operation and was measured at 301 ps. Through simulation, the minimum safe clock period was found to be 1.28 ns, corresponding to a maximum operating frequency of 781 MHz. Power was measured by integrating the supply current during repeated write operations, yielding an energy cost of 1.673 pJ. The estimated array area is 2.07 µm².

Verification

All subsystems were individually verified, including tristate buffers, inverters, row decoder, and precharge control. The full SRAM array was then validated through comprehensive test cases that demonstrated correct read and write behavior, non-destructive reads, address switching, and repeated access to the same row without data loss.

Technical Highlights

• Designed and simulated a complete 16x4 SRAM array at the transistor level.
• Optimized row decoder and precharge circuitry to reduce fan-in delay and redundant logic.
• Measured power, delay, and area to compute a quantitative figure-of-merit.
• Validated functionality through detailed Cadence Virtuoso simulations of all read/write scenarios.

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AutoAlign

Designed an adaptive toy launcher platform as the final project for Embedded Systems/Microcontroller Lab.

Implemented SPI RF communication between dual ATmega microcontrollers and integrated PWM motor control and interrupt-driven sensor feedback for closed-loop targeting based on ADC input from a peripheral target system.

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Triangle Rasterizer & Perspective Camera

Project Overview

In this assignment for CIS 5600: Computer Graphics, I implemented a complete software rasterizer in C++ capable of rendering 2D and 3D triangle meshes without relying on OpenGL’s fixed-function pipeline. The project progressed from basic 2D triangle filling to full 3D rendering using a custom perspective projection camera, giving me low-level exposure to how modern graphics pipelines operate beneath the abstraction of GPU APIs.

2D Triangle Rasterization

I first implemented a scanline-based rasterization algorithm to fill arbitrary 2D polygons composed of triangles. This included computing pixel-row intersections with triangle edges, handling all intersection cases robustly, and determining pixel coverage using barycentric interpolation. Care was taken to avoid early rounding, clamp output colors correctly, and ensure edge cases did not introduce visual artifacts such as missing rows or horizontal gaps.

3D Projection Pipeline

After validating 2D rasterization, I extended the system to support 3D triangles by building a full camera transformation pipeline. Vertices in world space were transformed through view and projection matrices into screen space, then rasterized using the same barycentric framework. This required careful handling of homogeneous coordinates, perspective division, and correct matrix construction using column-major ordering conventions.

Shading and Attribute Interpolation

To render color and texture correctly across 3D triangles, I implemented perspective-correct barycentric interpolation. All interpolation was performed in screen space after depth values were computed, ensuring that color gradients and texture coordinates behaved consistently even under extreme perspective distortion.

Technical Highlights

• Built a full CPU-based triangle rasterizer for both 2D and 3D scenes.
• Implemented scanline filling, edge intersection logic, and barycentric point-in-triangle testing.
• Constructed a complete camera pipeline including world, view, and projection transformations.
• Added perspective-correct interpolation for per-pixel color and texture attributes.
• Developed the system using C++ with Qt for GUI display and image output.

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Custom PCB-Based Analog Metal Detector

Project Overview

This metal detector project, built for the final lab in ESE 3190: Fundamentals of Solid-State Circuits, integrated multiple circuit design concepts covered throughout the semester. The final deliverable was a fully functional, PCB-based metal detector that used frequency modulation to detect the presence of nearby metal objects. The system incorporated analog components including oscillators, mixers, amplifiers, and filters, with each block thoroughly simulated in LTSpice and validated through physical measurements.

System Design and Signal Flow

The metal detector operates by generating two sinusoidal signals using LC oscillators—one with a fixed frequency and one variable based on environmental inductance. These signals are then mixed to produce a difference frequency, which increases in the presence of metal. The resulting low-frequency signal is amplified and driven into a speaker, producing a high-pitched sound when metal is near.

Key Circuit Blocks

Oscillator Stage

Two LC oscillators—one fixed at ~50 kHz, the other variable near ~53 kHz—generate the base signals. The variable oscillator responds to changes in nearby metal through induced eddy currents.

Mixer Stage

A differential amplifier combined with CS amplifiers and a low-pass filter mixes the signals and extracts their frequency difference (~2–5 kHz), which lies in the audible range.

Amplification and Output

The difference signal is boosted with a CS amplifier, buffered with a CD amplifier, and sent to an 8Ω speaker. The sound pitch rises in response to nearby metal.

PCB Design and Fabrication

A custom PCB was created to implement the full system reliably. The board segmented each block (oscillators, mixer, amplifiers) for modular testing and included labeled test points for oscilloscope validation.

Technical Highlights

• Accurate hand calculations and SPICE simulations were used to predict oscillator frequencies and amplifier gains.
• LTSpice was used to tweak component values, and simulations were verified with physical measurements.
• Demonstrated application of transistor biasing, analog gain stages, and frequency-domain filtering in a practical embedded system.

Construction and Assembly

The final implementation required careful soldering and assembly of the PCB components, followed by thorough testing and calibration of the system.

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Electric Utility Truck Project

Project Overview

This electric utility vehicle was designed and built from the ground up for use by my school's maintenance department. While the original concept came from two graduating seniors, I independently took the project forward—redesigning, rebuilding, and ultimately completing the truck.

Battery

The truck is powered by a custom-built 72V lithium-ion pack consisting of a 20s30p configuration of 18650 cells.

I configured a compatible Battery Management System (BMS) to monitor pack health, cell voltage, and temperature. This involved careful planning of wiring topologies, grounding strategies, and data connections. Proper balance, safety, and high-current output were critical for reliable performance.

Charge Control

The charging subsystem presented some of the most complex debugging challenges. I set up CAN-based communication between the charger, BMS, and charge controller, configuring each module to report and respond to power flow and safety events.

At one point, I tracked down a persistent charging error to a floating ground reference—a subtle but critical issue that highlighted the importance of circuit grounding in high-voltage systems.

Motor Control

The truck uses dual 2000W hub motors, optimized for high torque output with a capped top speed of 30 km/h, perfect for campus use.

Each motor is controlled via an independent controller, and system calibration required both software configuration and physical signal routing.

Chassis Fabrication and Mechanical Build

Beyond electrical systems, I also did the mechanical construction of the vehicle. This included designing and welding custom axle mounts, improving my welding technique and structural design skills along the way. The frame needed to withstand rugged daily utility use, so I focused on both strength and accessibility for maintenance.

Final Result

By the end of the build, the truck was fully operational and I was able to drive it around campus. The project not only gave me hands-on experience in EV system design but also pushed me to learn practical fabrication, embedded communication protocols, and high-power electrical safety.

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Game Design Portfolio

A collection of educational and entertainment games developed over the years, showcasing my journey in game development from Processing to Unity.

Planar Trainer

Recognizing the need for accessible Algebra II practice resources, I developed Planar Trainer using Unity. This educational game provides an interactive platform for students to practice linear equations, graphs, quadratics, and polynomials in an engaging format.

Pistol

May 2020

A Unity-based first person shooting game developed in C#, focusing on aiming precision

Blocks Away!

January 2020

An engaging endless block dodging game created in Unity using C#, featuring dynamic gameplay mechanics and progressive difficulty.

Carcade

October 2019 - My First Game

Developed using Java, this was my first foray into game development. A simple but engaging arcade-style game that taught me the fundamentals of game design and programming.

Meteor!

November 2020

A space-themed game built with Python using PyGame and Pymunk libraries, combining physics simulation with classic arcade gameplay elements.